Input/Output pads, also known as I/O buffers, are used in many integrated circuit applications. Conventional I/O pads typically include push/pull buffer configurations that include, for example, an output driver pull-up circuit and an output driver pull-down circuit. I/O pads are often connected to internal or external or off-chip pads on printed circuit boards or other integrated circuits. The I/O buffers are connected to other circuits through transmissions lines, such as printed circuit boards traces or any other suitable transmission lines. As is known in the art, transmission line signal distortions can result from impedance mismatches between the output buffer circuitry and the transmission line impedance. These signal distortions can vary due to fabrication process variations, temperature variations and other variations. Accordingly, I/O buffers have been designed to match the output impedance of the buffer with the transmission lines impedance. Without proper impedance matching, overshooting, undershooting and signal distortion can occur, particularly at high speeds. Further, an output pad may be required to drive multiple inputs. As a result, the drive strength of the output buffer requires adjustment accordingly.
Conventional solutions typically incorporate the use of off-chip components to implement matching termination networks. However, these can take up large amounts of space on the integrated circuit. Other, on-chip solutions require the use of separate test I/O pads for determining suitable impedance matching. For example, one external test pad is typically used to determine the suitable pull-up circuit impedance, whereas a separate additional test pad is used to determine suitable impedance matching for the pull-down circuit of the output buffer. In addition, separate external impedance calibration resistors are used for each I/O buffer section. The use of additional test pads and external resistors can impact board density, reliability and cost.
According to one embodiment, an on-chip impedance matching network provides a type of controlled impedance I/O pad by controlling a serially connected resistive element separate from the output drivers. For example, an array of programmable resistors in the form of parallel coupled transistors are controlled by on-chip calibration circuitry to program an on-chip impedance array by turning on and off various combinations of NFET transistors using an up/down counter. An external calibration resistor is connected to an internal chip pad. A differential amplifier is used to compare the internal pad voltage to a reference voltage. A difference between input voltages of the differential amplifier is perceived as a resistance mismatch between the external calibration resistor and the resistance of the transmissions line. The differential amplifier's output is programmed as an up/down counter to increase or decrease an output. The calibration is typically continuous. The method uses a separate programmable resistor array for each of a pull-down section and a pull-up section of an output buffer. However, this can unnecessarily increase the complexity and cost of the impedance matching circuit.
Other methods employ a plurality of external calibration resistors to duplicate the output buffer structure as the impedance compensation structure. Where two test pads and two external calibration resistors are used, the pull-up circuit, such as a P channel-based pull-up circuit, and an N channel output buffer pull-down circuit are typically independently tested and matched during normal operation of the chip. However, using dual calibration resistors can generate unnecessary internal noise. Known programmable impedance matching circuits effectively duplicate the structure of an I/O buffer, and the actual I/O buffer includes corresponding programmable resistor arrays that are then programmed to be identical to the impedance level determined through the I/O buffer impedance matching circuit. Typically, such I/O buffer impedance compensation circuits use, for example, an external pull-up calibration resistor that has an impedance equivalent to the line impedance to determine an appropriate impedance setting for the I/O pull-down circuit. Similarly, an external pull-down calibration resistor is coupled to ground and is used to determine a suitable impedance level for the pull-up circuit.
According to another method, an impedance compensation circuit for an I/O pad provides dynamic impedance compensation by using programmable impedance arrays and a dynamically adjustable on-chip load. Only a single off-chip calibration resistor is used, and only a single test pad is necessary. According to this method, all the I/O pads are calibrated to the same output drive strengths. However, memory interface pads, for example, typically require different output drive strength calibration for different groups in a channel. These interface pads, such as memory interface pads, may also require different drive strength calibration for different channels. As a result, all the I/O pads are calibrated with the same calibration setting, resulting in suboptimum calibration settings for some I/O pads.
According to another method, separate impedance controllers and impedance matching calibration circuits may be implemented for each of the different types of pads, such as memory pads. However, implementing separate impedance controller circuits and impedance matching calibration circuits would be an inefficient use of the limited number of transistors on an integrated circuit chip, and, further, would be expensive.